tarlan_heat

In addition of the EISCAT-standard TXSYNC and REP commands, there are the following TARLAN commands for the Heating transmitter radar controller.

Note that in TARLAN compiler version 2 or higher, the commands are case-insensitive, and can be separated either by a comma, or one or more spaces.

UPDspec --Update DDS parameters

This command reads a block of amplitude-phase-frequency parameters from each of the indicated RAMs and writes them into the corresponding DDS units on the exciter board, as specified by spec. Both DDS units on the implied exciter board are affected simultaneously.

The data read-write operation from RAM to DDS unit is pipelined in the following way, per each DDS unit. First, the value (or values; one of each of three word types) currently latched to the DDS unit's input buffer is transferred into an appropriate register on the DDS chip and is taken into use. This is achieved by generating a so called IOUPDAT signal to the DDS chip (see AD9953 data sheet ). Second, transfer of the next block of bytes from the RAM to the DDS input buffer is initiated; the transfer then proceeds autonomously through a bit-serial channel, driven by onboard logic. The RAM contents must have been loaded separately using the Eros loaddds command; typically, from a so called .paf file which specifies phases (3 bytes per value), amplitudes (3 bytes) and frequencies (5 bytes) to be loaded. See the Eros documentation of loaddds for details about .paf files. A block-to-be-transferred can contain up to 11 bytes, which is enough to specify all the three types of words in a single block. The serial transfer takes 40 ns per bit, so that an 11 byte transfer requires 11*8*40 ns = 3.5 microseconds for the actual transfer, plus a start-up overhead of about 0.2 microseconds, that is, about 3.7 microseconds. (All blocks loaded from a single .paf file will have the same length, specified in the .paf file itself; but there is a two-byte NOP instruction for padding.) The TARLAN programmer must ensure that no new transfer command is given while a transfer is going on, the compiler currently does not check this. Third, the RAM address counter is incremented to point to the beginning of next block in the RAM. The actual destinations in the DDS chip are encoded into the transferred data block itself, as the amplitude scaling factor (ASF), the frequency tuning word (FTW) or the phase offset word (POW) of the chip.

The exciter board can be specified in various ways:

spec = m1&2 | t1&2 | t3&4 | t5&6 | t7&8 | t9&10 | t11&12
spec = *, which means "all"
spec = t*, which means "all but m1 and m2"
spec = m*, which means "m1 and m2", thus, this is same as "m1&2".

For example, the TARLAN command

AT 10 UPDm* UPDt3&4

transfers a parameter from the two RAMs on the exciter master board m to the DDS units m1 and m2, and transfers data from the two RAMs on the exciter board b2 to the DDS units t3 and t4, on that board.

Note that even though the UPD command updates both DDSs on a board simultaneously, the RAMs are separate and can have different contents.

STMCspec --Initialize data transfer from RAM to DDS

Originally, this command did everything that an UPD command did, and in addition, reset the RAM address counters on the exciter board specified by spec. However, it was found out that having two different originators for the IOUPDAT signal caused impossible-to-control timing problems which showed up as a frequency drift between different DDS units when frequency modulation was used. (These issues are documented in a 2011 note by JM.) Therefore, exciter firmware was modified so that the STMC command does not cause an IOUPDAT signal to be generated at all; only the data transfer and the address reset. If an IOUPDAT is required with connection of a STMC instruction, an UPD instruction must be explicitly coded for the same instant of time in the TARLAN file. In that case, operations are internally arranged so that only a single data transfer from the RAM towards the DDS unit is launched. An additional benefit from the firmware modification is that it is now possible to properly initialise the transfer pipeline with the first value in the RAM, without causing "rubbish" (old, possibly unwanted data) to be transferred to the DDS at the same time.

The two DDS units on the board have their own modulation RAM; the STMC command affects both of them simultaneously. The spec specifies the board as in the UDP command. For example, the TARLAN command

STMCt*

resets the RAM address counters on all exciter boards except the master board, and the command

STMCt1&2,STMCt3&4

resets the RAM address counters on exciter boards b1 and b2, which control the transmitters T1, T2, T3 and T4.

PROFSELk --Select profile

Select the profile k (k=0-3) on both DDS units on all exciter boards. Each DDS unit has some onchip memory, separate to the "modulation RAM". However, loading of this memory is not currently implemented in Eros, so this command should not be used in the tlan files either.

RFONspec, RFOFFspec --Turn RF on, off

This command controls the SOUSY switch, and enables or disables the RF drive to the pair of transmitters specified by spec.

spec = 1&2 | 3&4 | 5&6 | 7&8 | 9&10 | 11&12
spec = *, which means "all"

For example, the command

RFON5&6

turns RF drive on for transmitters T5 and T6, and the command

RFON* RFOFF3&4

turns RF drive on for all transmtters T1...T12 except T3 and T4.

FLPspec --Phase flip on

NOFLPspec --No phase flip

Introduce, or not, an extra 180 phase flip for the pair of transmitters specified by spec. These commands controls the SOUSY switch.

spec = 1&3 | 2&4 | 5&7 | 6&8 | 9&11 | 10&12
spec = *, which means "all"

Note that the pairing is different from that used with the RFON|RFOFF commands. The purpose now is that each pair "m&n" corresponds to transmitters connected to same antenna dipole orientation. As seen in the figure, the odd-numbered transmitter units T1,3,5,7,9 and 11 are connected to antenna dipoles in the NE-SW orientation, while the even-numbered transmitter units are connected to dipoles in NW-SE orientation. Thus, for example, in

AT 1000 NOFLP*
AT 2000 FLP1&3,FLP5&7,FLP9&11

the phases of all the NE-SW dipoles in the array are flipped by 180 degrees at time 2000. This changes the handedness of circular polarization.

RXP1specON, RXP1specOFF -- Receiver protector 1 control

spec = A or B, or none.
If neither A nor B is specified, both protectors are controlled.

SBTXspec, CBTXspec, SBTXHhspec, CBTXHhspec -- Set and clear specified TX bit(s)

spec = bit, where bit is one of 0...31, this specifies an individual bit.
spec = bit-bit, this specifies a continuous range of bits.
hspec = hbit, where hbit is one of 0...5, this specifies an individual "high" bit.
hspec = hbit-hbit, this specifies a range of high bits.
Examples
SBTX31 --> set bit 31 --> leading edge of the positive TXSYNC pulse.
CBTX31 --> clear bit 31 --> trailing edge of the TXSYNC pulse.
SBTX0-6 --> set bits 0-6 --> leading edge of the positive UPD pulse on all DDS.
CBTX7-13 --> clear bits 7-13 --> leading edge of the negative STMC pulse on all DDS.
CBTXH0-5 --> clear all high bits.

TARLAN commands for the receiver radar controller

In addition of the EISCAT-standard CH1|2, CH1|2OFF, NCOSEL, STFIR, RXSYNC, BUFLIP, STC, and REP commands, there are the following TARLAN commands for the Heating receiver radar controller.

PSAVONspec --Turn TX power saving on

PSAVOFFspec --Turn TX power saving off

These commands turn on or off the power-saving feature of heating transmitters. Note that even though the command affects the transmitters, the command is generated by the receiver radar controller. Each of the six bits used controls a pair of transmitters.

spec = 1&2 | 3&4 | 5&6 | 7&8 | 9&10 | 11&12 | *

CHLmRn --Select A/Ds for the two receiver channels.

The heating receiver has two A/D converters AD1 and AD2, and two channel boards Ch1 and Ch2. Channel 1 is the left-hand channel on the VME rack and channel 2 is the right-hand channel on the rack. Each channel will always use one or the other of the A/Ds for input.

Examples
CHL1R1 --> ch1 uses AD1 and ch2 uses AD1
CHL1R2 --> ch1 uses AD1 and ch2 uses AD2
CHL2R1 --> ch1 uses AD2 and ch2 uses AD1
CHL2R2 --> ch1 uses AD2 and ch2 uses AD2

RXP2specON, RXP2specOFF --Receiver protector 2 control

spec = A | B |
If neither A nor B is specified, both protectors are controlled.

SBRXspec, CBRXspec, SBRXHhspec, CBRXHhspec -- Set and clear specified RX bit(s)

spec = bit, where bit is one of 0...31, this specifies an individual bit.
spec = bit-bit, this specifies a continuous range of bits.
hspec = hbit, where hbit is one of 0...5, this specifies an individual "high" bit.
hspec = hbit-hbit, this specifies a range of high bits.
Examples
SBRX31 --> set RX bit 31 --> leading edge of the positive RXSYNC pulse.
CBRX31 --> clear RX bit 31 --> trailing edge of the RXSYNC pulse.
CBRX10-11 --> clear RX bits 10-11 --> both receiver channels ON.
SBRXH0-5 --> set all RX high bits --> power saving OFF on all TX modules.

Options

-v
Verbose. Use -vv and -vvv for even more verbosity.
-t
Compile for transmitter, creating only transmitter output files.
-r
Compile for receiver, creating only receiver output files.
-a
Generate .rasc and .tasc files, using both bin and hex formats. If none of -abx is specified, no asc files are generated.
-x
Generate .rasc and .tasc files, using only hex format.
-b
Generate .rasc and .tasc files, using only binary format.
-f infile
This specifies the source (.tlan) file. The source can be also specified as a command argument, without the -f.
-o outpath
Set output path root name, so that output files become outpath.tbin, etc. If this option is not specified, the outpath is picked from the infile.
-T
Test mode. Compilation only, no output files are generated.

Table of Contents

• Synopsis
• Description
  • Transmission control under TARLAN
  • TARLAN commands for transmitter radar controller
  • TARLAN commands for the receiver radar controller
• Options